Verification / Senior Verification Engineer
Level inferred from job title
Job description
A Verification / Senior Verification Engineer role at Riverlane, joining a team of hardware designers and embedded software engineers to deliver fully verified, high-performance, trusted systems. The role owns verification planning and strategy across block-level and system-level designs.
At a glance
- Employment
- Full-time · Employee (employment agreement)
- Work mode
- Hybrid
- Pay
- GBP 60,000 – 88,000 / year
What you'll do
- Proactively work with designers and architects to define verification plans based on design specifications, taking full ownership of detailed test strategies across block-level and system-level designs
- Develop and implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog; implement self-testing, directed and random tests
- Maintain the health and evolution of the design verification environment, tracking regressions, coverage metrics and bugs
What we're looking for
- Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy
- Proven experience of testbench design with verification frameworks like UVM/OVM
- Knowledge of SystemVerilog assertion (SVA)
- Exposure to different programming languages, such as C, C++ and Python
- A proactive person who can independently define the scope of work
- A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback
- Ability to work effectively with ambiguity and changing requirements
- Experience debugging across RTL, simulation, and hardware
Nice to have
- Formal verification experience
Your team
hardware designers and embedded software engineers
A talented team of hardware designers and embedded software engineers delivering fully verified, high-performance, and trusted systems.
Benefits
- Annual bonus plan
- Private medical insurance
- Life insurance
- Contributory pension scheme
- Equity
- 28 days annual leave, plus bank holidays and enhanced family leave
- A diverse work environment with experts in many fields and over 20 different nationalities
- A learning environment with a regular programme of learning events and training and conference budgets
Apply
Direct apply at Riverlane
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About Riverlane
World leader in quantum error correction technology
Riverlane is the world leader in QEC technology, having raised more than $125M in funding to date to accelerate cutting-edge R&D in quantum error correction. Riverlane partners with many of the world's leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality.
Mission
To master quantum error correction (QEC) and unlock a new age of human progress.
Key facts
- Quantum computing
- Raised more than $125M in funding to date
- Partners with many of the world's leading quantum hardware providers and government agencies
- Team includes experts in software and hardware development, quantum information theory, physics and maths, and over 20 different nationalities