Analog Layout Engineer (Lead)
Job description
Lead Analog Layout Engineer responsible for custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high-speed chip-to-chip communication links (SerDes and/or memory IO) in advanced semiconductor nodes. The role involves close collaboration with the design team, IP/chip-level integration, and customer interaction.
At a glance
- Work mode
- Remote · EU, United Kingdom
What you'll do
- Custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes
- Layout and verification of very high-speed analog circuits
- Interact closely with the design team to understand requirements and implement solutions
- Support IP and chip level integration
- Support and interact with customers on requirements, and IP delivery
- Exposure to flip-chip package technologies
What we're looking for
- 10-15 years of relevant experience
- Must have experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits
- Must have expertise in layout of high-speed/frequency circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc.
- Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements
- Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
- User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc.
- Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
- Manage workload and schedules and report to internal management team
- Background in Semiconductor Physics
- Graduate in E.E.
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About Kandou AI
Redefining the economics of AI infrastructure
Kandou's proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, the solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Mission
Democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Key facts
- AI infrastructure / semiconductor hardware
- Proprietary MIMO-over-copper technology
- Chiplet-based AI memory fabric
- Reduces power consumption significantly while preserving high bandwidth and ultra-low latency
- Architecture described as a foundational shift in how AI hardware is built