Advanced Packaging & Power Delivery Senior Engineer

Axelera AI

Contract type

Ongoing

Work mode

100% remote

Experience

Senior · 7+ years

Job description

Own power-delivery design end to end, from on-die power grids to package and PCB PDN design and analysis
Lead advanced packaging architecture decisions for 2.5D/3D stacking, multi-chiplet integration, and interposer/substrate co-design
Perform SI/PI verification and sign-off across the full stack, ensuring power integrity and signal integrity targets are met
Collaborate with the AIIS and Silicon Engineering teams to align power delivery and packaging solutions with product and silicon requirements
Support thermal and integration reviews for current and future products
Develop and maintain power-delivery methodology, flows, and design guidelines within the Custom Design toolchain
Identify and mitigate single-point-of-failure risks in SI/PI workstreams; mentor and grow the team's packaging expertise
Engage with external partners, substrate/interposer vendors, and OSAT houses to co-develop advanced packaging solutions
Company mission
Information not specified

Flexible working arrangement, with options to work fully remotely from any European country (incl. the UK) you are already in
Relocation support to work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven)
Chance to shape and be part of a dynamic, fast-growing, international organization

Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related field; PhD is a plus
7+ years of experience in power delivery and/or advanced packaging design in a semiconductor or deep-tech environment
Demonstrated expertise in on-die power grid design and package/PCB PDN analysis
Hands-on experience with 2.5D and/or 3D IC packaging technologies, multi-chiplet integration, and interposer/substrate co-design
Proficiency with industry-standard EDA tools for power integrity, PDN simulation, and package design
Ability to work cross-functionally and communicate complex technical trade-offs to diverse stakeholder groups
Strong written and spoken English communication skills
experience with SI/PI verification and sign-off methodologies
familiarity with thermal modeling and co-simulation for integrated packages
exposure to AI accelerator or custom ASIC design flows
experience collaborating with OSAT partners, substrate vendors, or research institutes (e.g., imec)
knowledge of advanced node custom and analog design practices
Information not specified
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